Silicon carbide (that will be referred to as SiC) has a wide band gap, and its maximum breakdown electric field is larger than that of silicon by one order of magnitude. Thus, SiC has been highly expected to be used as a material for power semiconductor devices in the next generation. Up to the present, various types of electron devices, in particular, those for switching large power at high temperatures, have been developed, using single-crystal wafers, such as 4H-SiC and 6H-SiC. These crystals are alpha-phase SiC in which a zinc-blend structure and a wurtzite structure are superposed on each other. Also, semiconductor devices have been fabricated using crystals of beta-phase SiC, such as 3C-SiC.
Recently, power devices, such as Shottky diodes, vertical MOSFET, and thyristors, and CMOS-IC as the most general semiconductor devices, have been fabricated using SiC as a semiconductor material, and it has been confirmed that these devices exhibit far better characteristics than conventional Si semiconductor devices, as reported by Weitzel, C. W. et al.: IEEE Trans. on Electron Devices, vol. 43, No. 10, pp. 1732-1741 (1997). Some examples of MOSFET will be now illustrated.
FIG. 13 is a cross-sectional view of a unit cell of a junction type FET (that will be abbreviated to JFET) that has been developed as a high-frequency device (Sheppard, S. T. et al: Abstract of Int. Conf. on Silicon Carbide, III-Nitrides and Related Materials, (1997)). In this device, an n drift layer 11 is laminated on a p.sup.+ substrate 10, and n.sup.+ source region 13, p gate region 15 and n.sup.+ drain region 14 are formed in a surface layer of the n drift layer 11. Further, source electrode 17, drain electrode 18, and gate electrode 16 are formed in contact with the n.sup.+ source region 13, n.sup.+ drain region 14, and the p gate region 15, respectively.
With this arrangement, when a voltage is applied to the gate electrode 16, a depletion layer spreads from the p gate region 15 to an n channel region 20 defined between the p gate region 15 and the p.sup.+ substrate 10. As a result, current flow between the source electrode 17 and the drain electrode 18 is restricted. By removing the voltage applied to the gate electrode 16, current flows again between the drain electrode 18 and the source electrode 17. Thus, the device is capable of switching current between the source and drain electrodes, by controlling the gate voltage. This type of JFET is called a "depletion type" since the channel region is depleted upon application of voltage to the gate electrode 16. A groove is formed which extends from the surface of the semiconductor substrate to the p.sup.+ substrate 10, and is filled with an insulator film 19, so as to isolate adjacent devices.
FIG. 14 shows one type of vertical MOSFET (Shenoy, J. N., et al, Abstract of Int. Conf. on Silicon Carbide, III-Nitrides and Related Materials, (1997)). To produce the MOSFET, an n drift layer 21b is laminated on an n.sup.+ substrate 21a, and a p.sup.+ embedded region 22 is formed in the n drift layer 21b by implanting ions with a high accelerating-field voltage. Also, an n.sup.+ source region 23 is formed in a surface layer of the n drift layer 21b located above the p.sup.+ embedded region 22. A gate electrode layer 26 is formed on a gate insulating film 25 that is in turn formed on the surface of a portion of the n drift layer 21b that is interposed between two n.sup.+ source regions 23. A source electrode 27 is formed on the surface of the n.sup.+ source region 23, and a drain electrode 28 is formed on the rear surface of the n.sup.+ substrate 21a.
In this example, the gate portion does not have a pn junction, but has a MOS structure to which a voltage is applied via the gate insulating film 25. In the MOSFET, when a positive voltage is applied to the gate electrode layer 26, an accumulation layer is induced in an n channel region 30 in a surface portion of the n drift layer 21b right below the gate electrode 26, and current flows between the drain electrode 28 and the source electrode 27. When a negative voltage is applied to the gate electrode 26, current flow between the drain electrode 28 and the source electrode 27 is interrupted or stopped. Thus, the MOSFET has a switching function. The voltage between the source and the drain is also applied to the p.sup.+ embedded region 22 and the n drift layer 21b, so that the device can hold a large voltage, thus assuring a high breakdown voltage. The MOSFET is also called ACCUFET since the accumulation layer is formed upon application of a voltage to the gate electrode 26.
FIG. 15 is a cross-sectional view of a unit cell of another type of vertical high-voltage MOSFET (Onda, S. et al., Phys. Stat. Sol. (a), vol. 162, p. 369, (1997)).
In the MOSFET, a p base region 32 is formed in a surface layer of an n drift layer 31b that is laminated on an n.sup.+ substrate 31a, and an n.sup.+ source region 33 is formed on a surface layer of the p base region 32. Also, an n channel region 40 that connects two n.sup.+ source regions 33 is formed by epitaxial growth, and a gate electrode layer 36 is formed above the surface of the n channel region 40, with a gate insulating film 35 interposed therebetween. A source electrode 37 is formed on the surface of the n.sup.+ source region 33, and a drain electrode 38 is formed on the rear surface of the n.sup.+ substrate 31a.
In this case, too, when a positive voltage is applied to the gate electrode layer 36, an accumulation layer is induced in a surface portion of the n channel region 40 right below the gate electrode layer 36, and current is allowed to flow from the drain electrode 38 to the source electrode 37. When a negative voltage is applied to the gate electrode layer 36, the current flow between the drain electrode 38 and the source electrode 27 is interrupted or stopped. Thus, the device performs a switching function by controlling the voltage applied to the gate electrode layer 36.
While other examples of MOSFET, such as those of planar type or trench type, may be produced using SiC substrates, it has been found from experiments that the mobility of carriers in an inversion layer of SiC is considerably small, and therefore SiC substrates are not suitable for practical use in enhancement type FET using inversion layers.
On the other hand, the devices of the above three examples are not enhancement type FET using inversion layers, but operate as FET using semiconductor layers of the original conductivity type as channels. Thus, the structures of the above examples are suitable for use with SiC.
Although semiconductor devices for power switching having the structures of FIGS. 13, 14 and 15 are expected to exhibit remarkably excellent characteristics, actual SiC devices have not realized such excellent characteristics, or such devices have not been actually manufactured.
One of the reasons is that the double-diffused MOS (D-MOS) structure that has been widely employed in Si semiconductors cannot be easily applied to SiC. In Si substrates, p-type impurities and n-type impurities are introduced into selected regions using the same mask, and then thermally diffused, so as to achieve a desired channel density with high accuracy. Namely, the dimensions of channels that greatly influence the characteristics of MOSFET can be controlled with high accuracy, thus assuring high yield in the manufacture of MOSFET.
On the other hand, impurities introduced into SiC by ion implantation are less likely to be activated, namely, the impurities thus introduced have a low activation rate. In order to improve the activation rate, the ion implantation needs to be conducted at 1000.degree. C. or higher, and heat treatment for activation needs to be conducted at 1600.degree. C. or higher. Also, the impurities introduced by ion implantation hardly diffuses in SiC substrates. For these reasons, p-type impurities and n-type impurities must be respectively introduced using different masks, making it difficult to control the channel density with high accuracy. The resulting MOSFET has large channel resistance with considerably large variations, and the resistance of the device as a whole is mostly determined by the channel resistance. This makes it difficult for SiC to exhibit its inherent characteristics.